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UMC and partners targets edge AI with W2W 3D IC project launch

UMC and partners targets edge AI with W2W 3D IC project launch

Semiconductor foundry, United Microelectronics Corporation (UMC) has initiated its W2W (wafer-to-wafer) 3D IC project in collaboration with partners Winbond, Faraday, ASE, and Cadence.

With the aim of helping its customers boost their 3D products, the project offers an end-to-end solution for integrating memory and processor with silicon stacking technology.

The company says the project aims to cater to the demand for efficient computing at the device level as artificial intelligence expands from cloud to the edge.

“Through this cross-supply-chain vertically integrated project, we are excited to work with industry leaders to enable customers to leverage our advanced hybrid bonding W2W technology, to enjoy the inherent performance gain, form factor reduction, and cost benefits of 3D IC,” says G C Hung, vice president of the result delivery office and research development at UMC.

“Heterogeneous integration will continue to push the boundaries of semiconductor innovation in the More-than-Moore era, and UMC looks forward to contributing our robust CMOS wafer manufacturing capabilities together with advanced packaging solutions to the development of a complete ecosystem.”

The W2W 3D IC project with partner collaboration targets edge AI applications, such as home and industrial IoT, security, and smart infrastructure – requiring mid-to-high range computing power, customizable memory modules, and low power consumption.

“As AI continues to move beyond data centers to the edge, edge devices will require higher memory bandwidth in order to handle the increase in data workloads,” adds Hsiang-Yun Fan, DRAM vice president of Winbond.

“Winbond is honored to be the memory supplier for this project with our Customized Ultra-Bandwidth Elements (CUBE), which will enable customers to incorporate customized DRAM into their 3D packages for optimal edge AI performance.”

According to the company, it will resolve various heterogeneous integration challenges including alignment of wafer stacking rules between logic and memory fabs, design flow for vertical wafer integration, and a proven package and testing path.

Speaking about the project, Don Chan, vice president, R&D in the digital & signoff group at Cadence, says: “With the continued proliferation of edge AI applications, 3D IC design is becoming increasingly crucial for our customers. As the only EDA partner in this new project, we’re working closely with Faraday and UMC to enable 3D IC designs with the Cadence Integrity 3D-IC Platform. We are committed to enabling faster time-to-market designs for our customers.”

UMC will focus on CMOS wafer manufacturing and wafer-to-wafer hybrid bonding technology, Winbond will introduce Customized Ultra-Bandwidth Elements (CUBE) architecture for edge AI devices, and Faraday offers turnkey services for 3D advanced packaging, as well as memory IP and ASIC chiplets design services.

“Faraday is proud to be a founding member of the 3D IC project,” says Flash Lin, COO of Faraday.

“We are already working closely with UMC and best-in-class OSAT suppliers for our 2.5D/3D advanced packaging service, and this project is an important extension of that to empower customers in harnessing the endless potential of chip integration.”

Cadence will focus on wafer-to-wafer design flow, extraction with through-silicon vias (TSVs), and sign-off certification, while ASE will offer die sawing, packaging, and testing services.

“As part of a dynamic ecosystem, ASE is committed to collaborating with industry partners in order to empower our customers to optimize efficiencies in their semiconductor design and manufacturing process,” notes Dr. C.P. Hung, vice president of R&D, ASE.

“This project helps us collectively to improve customer time-to-market and sustain profitable growth through the integration technologies developed to accomplish application excellence in the AI era.”

The platform is expected to be ready in 2024 following the completion of system-level verification.

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