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Researchers develop 2D transistors for in-memory computing as the future of embedded devices

Categories Edge Computing News  |  Hardware
Researchers develop 2D transistors for in-memory computing as the future of embedded devices

Scientists have actively searched for the ideal materials and devices to construct an in-memory computing system. They have explored options such as resistive random access memories (ReRAM) and ferroelectric memories (FeFET). However, recent advancements in two-dimensional materials, particularly those pertaining to beyond-CMOS devices and in-memory and in-sensor computing, have introduced materials such as monolayer MoS2 that exhibit the potential to create efficient in-memory processors.

A group of researchers associated with École Polytechnique Fédérale de Lausanne in Switzerland have demonstrated the development of a floating-gate field-effect transistor (FGFET) based on monolayer MoS2. These transistors can be scaled to build processors of varying sizes and complexities. The researchers highlight that these monolayer MoS2-based FGFETs have the capacity to enhance power efficiency when compared to traditional CMOS-based circuits.

The large-scale integration incorporates a 32×32 vector-matrix multiplier. To facilitate the construction of larger arrays of FGFETs, they are arranged in a matrix format, which allows the selection of specific memory elements by choosing the appropriate row and column. This matrix arrangement also results in a more compact layout and is particularly ideal for executing vector-matrix multiplication. The chip is designed with 1024 FGFETs.

“We demonstrate reliable, discrete signal processing in a highly parallel manner. Our findings set the grounds for creating the next generation of in-memory processors and neural network accelerators that can take advantage of the full benefits of semiconducting van der Waals materials for non-von Neuman computing,” the researchers add.

In the context of the growing adoption of IoT and edge computing technologies in remote locations, the conventional von Neumann computer architecture, which separates memory and logic units, is seen as a significant challenge to computational efficiency. This separation necessitates frequent data transfers between memory and processing units during computational tasks, resulting in a substantial energy expenditure. To address these limitations and enhance energy efficiency, in-memory computing architectures have been introduced.

“The processing-in-memory devices are especially suitable for performing vector-matrix multiplication, which is the key operation for data processing and the most intensive calculation for implementing machine-learning algorithms. By taking advantage of the memory’s physical layer to perform the multiply and accumulate operation (MAC), this architecture overcomes the Von-Neumann communication bottleneck,” explains the researchers.

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